1. Field of the Invention
The present invention relates to a semiconductor device configured to have, for example, a resistor element with parasitic capacitance as a structural component.
2. Description of the Related Art
In ordinary techniques, a resistor element is used as a voltage-division element or one of CR time constant elements in a power supply circuit for producing a constant potential or in a delay circuit for providing a signal delay within a semiconductor device. A resistor element has a resistance of a predetermined value between two nodes. In many cases, a resistor element of several-ten Ω to several-mega Ω is used. However, in an actual fabrication process of a semiconductor device, a resistor element with an ideal resistance component alone cannot be manufactured and a parasitic capacitance is inevitably added.
For example, in a case where an N-type impurity diffusion layer region is formed on a P-type semiconductor substrate and it is used as a resistor element, a parasitic capacitance is added to a node for connection with the resistor element due to a PN junction occurring between the P-type substrate and the N-type diffusion layer. Such a parasitic capacitance occurring in the resistor element fabrication process may lead to an unstable circuit operation, as described below.
FIG. 1 is a circuit diagram of a conventional semiconductor device using resistor elements formed on a semiconductor substrate. The semiconductor device shown in FIG. 1 is a semiconductor device that is used by effecting switching between two modes, an active mode and a standby mode (i.e. inactive mode).
In FIG. 1, in the active mode, switches SW1 and SW2 are closed, and an output voltage VOUT is resistor-divided by two resistor elements ra1 and rb1 each having a low resistance value. The divided voltage is supplied as a reference potential to a reference node NREF. The reference potential is compared with a fixed potential VFIX by a comparison circuit 100. A comparison output is delivered to the gate of a PMOS transistor 101 that functions as an output adjusting element. Thereby, an output voltage VOUT corresponding to the active mode is produced.
If the output voltage VOUT varies due to some cause, e.g. a variation in load, an influence of the variation appears at the reference node NREF as a reference potential variation and is fed back to the comparison circuit 100. In this way, a control to keep the output voltage VOUT constant is performed.
When the semiconductor device is in the active mode, as described above, the output voltage VOUT is controlled by the low-resistance resistor elements ra1 and ra2. When the semiconductor device is in the standby mode, the switches SW1 and SW2 are opened and the standby mode is set in a low power consumption state using resistor elements RS1 and RS2. However, when the active mode transits to the standby mode, as shown in FIG. 1, the following problem occurs due to parasitic capacitance added to each resistor element. The problem is explained referring to FIG. 2.
FIG. 2 is an equivalent circuit diagram for explaining an adverse effect on the circuit operation due to a parasitic capacitance in a case where there is a difference (high/low relationship) in resistance value between the low-resistance resistor elements ra1 and ra2 in the circuit shown in FIG. 1 and accordingly there is a difference in parasitic capacitance.
When the semiconductor device is switched from the active state to the standby state, as shown in FIG. 2, the switches SW1 and SW2 are opened and no current flows through the low-resistance resistor elements ra1 and ra2. However, since there are parasitic capacitances in the resistor elements ra1 and ra2, an accumulated charge of the parasitic capacitances may, in some cases, be discharged through the resistor element RS1, etc.
For example, when the resistance value of the resistor element ra2 is higher than that of the resistor element ra1, the diffusion area of the resistor element ra2 is accordingly larger in usual cases, and thus the parasitic capacitance of the resistor element ra2 is higher than that of the resistor element ra1. Hence, a charge C1, which flows from the parasitic capacitance of the resistor element ra2 to the high-resistance resistor element RS1 via a node connected to the reference node NREF, is greater than a charge C2 flowing from the reference node NREF side toward the parasitic capacitance of the low-resistance resistor element ra1. Both charges C1 and C2 do not cancel each other. As a result, the potential at the reference node NREF rises, and the control of the output voltage VOUT in the standby mode becomes unstable.
FIG. 3 is a circuit diagram of another conventional semiconductor device using a resistor element with a parasitic capacitance formed on a semiconductor substrate. The operation of the circuit shown in FIG. 3 is described referring to FIG. 4.
In FIG. 3, if the potential at an input terminal 113 rises from “L” (low level) to “H” (high level), a transistor 112 is turned on and a charge in a capacitor C connected to a node X is discharged via a resistor element R and the transistor 112. A time t needed for the discharge is approximately equal to a time constant (t˜RC) obtained by multiplying a resistance value R of the resistor element R by a capacitance value C of the capacitor C. A delay is intentionally added to the time for transmission of a signal from the input terminal 113 to an output terminal 114, by making use of the RC time constant.
When the potential at the input terminal 113 falls back to “L”, a transistor 111 is turned on and the potential at the node X is charged to “H” by a power supply voltage V. However, since a parasitic capacitance is added to the resistor element R, a predetermined time is needed to completely charge the entire resistor element R to the “H” level. The time needed for charging the resistor element R is approximately RCp, where Cp is a parasitic capacitance of the resistor element R and R is the resistance value of the resistor element R.
In the circuit of FIG. 3, if a time (reset time) in which the input to the input terminal 113 is “L”, that is, the potential at node X is “H”, is much shorter than the time constant RCp (reset time<<RCp), as shown in FIG. 4, the parasitic capacitance in the resistor element R is not fully charged to “H” (time period 14-1 in FIG. 4). As a result, the time period needed for the discharge of the charge accumulated at the node X after the input potential falls back to “L” becomes shorter than the time period in the case where the resistor element R is fully charged (time 14-2 in FIG. 4).
Consequently, depending on the length of time in which the input IN is held at “L”, a delay time between the input and the output will vary. In particular, if the time in which the input IN is held at “L” is short, the delay time would become short.